Title :
A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit
Author :
Ishii, Kiyoshi ; Kishine, Keiji ; Ichino, Haruhiko
Author_Institution :
NTT Network Innovation Labs., Kanagawa, Japan
Abstract :
This paper describes a jitter suppression technique for a 2.48832 Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique improves both the jitter generation and the jitter transfer function. The jitter generation can be suppressed by boosting the loop gain in PLL. A suitable jitter transfer function and jitter tolerance can be achieved by optimizing the characteristics of a surface acoustic wave (SAW) filter. The fabricated circuit had a low jitter generation (about 2.4 mUI rms) and a low jitter transfer function cutoff frequency (about 500 kHz) by using a SAW filter with a center frequency (fc) of 622.08 MHz. The jitter generations are within fc mUI rms for the temperature range between 0°C to 90°C. The circuit passes the jitter tolerance specification in ITU-T recommendation G.958 by more than 30%
Keywords :
bipolar integrated circuits; high-speed integrated circuits; mixed analogue-digital integrated circuits; optical receivers; optical repeaters; phase locked loops; surface acoustic wave filters; synchronisation; timing circuits; timing jitter; transfer functions; 0 to 90 C; 2.48832 Gbit/s; 622.08 MHz; ASIC; ITU-T recommendation G.958; PLL; Si; Si bipolar ICs; clock recovery; clock/data recovery circuit; data recovery; jitter generation; jitter suppression technique; jitter tolerance specification; jitter transfer function; loop gain boosting; phase-locked loop; surface acoustic wave filter; Acoustic waves; Boosting; Circuits; Clocks; Cutoff frequency; Filters; Jitter; Phase locked loops; Surface acoustic waves; Transfer functions;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857414
