Title :
Implementation of Nonlinear Template Runner Emulated Digital CNN-UM on FPGA
Author :
Kineses, Zoltan ; Nagy, Z. ; Szolgay, P.
Author_Institution :
Dept. of Image Process. & Neurocomputing, Pannonia Univ.
Abstract :
In the original CNN paradigm template values are defined as constants but several complex tasks can be efficiently solved by using nonlinear weights between the CNN cells. Unfortunately programmable nonlinear weights can not be implemented by using present day analog VLSI technology. In this paper a new emulated digital CNN-UM architecture will be presented which makes it possible to use zero and first order nonlinear templates during emulation. The new architecture is based on the Falcon emulated digital CNN-UM architecture and implemented on FPGAs. The computing precision of the architecture is configurable and the area/speed/accuracy tradeoffs are investigated
Keywords :
VLSI; cellular neural nets; field programmable gate arrays; CNN cells; FPGA; analog VLSI technology; cellular neural networks; emulated digital CNN-UM; field programmable gate arrays; first order nonlinear templates; nonlinear CNN template; nonlinear template runner; nonlinear weights; reconfigurable architectures; Application software; Cellular neural networks; Computer architecture; Detectors; Emulation; Field programmable gate arrays; Gray-scale; Hamming distance; Image processing; Very large scale integration; Cellular neural networks; Field programmable gate arrays; Nonlinear CNN template; Reconfigurable architectures;
Conference_Titel :
Cellular Neural Networks and Their Applications, 2006. CNNA '06. 10th International Workshop on
Conference_Location :
Istanbul
Print_ISBN :
1-4244-0639-0
Electronic_ISBN :
1-4244-0640-4
DOI :
10.1109/CNNA.2006.341627
