A DLL based 10-320 MHz clock synchronizer

Author

Hwang, Sung-Sik ; Joo, Ki-Mo ; Park, Ho-Jin ; Kim, Jae-Whui ; Chung, Philip

Author_Institution

Syst. LSI Div., Samsung Electron. Co., Kyungki, South Korea

Volume

5

fYear

2000

fDate

2000

Firstpage

265

Abstract

A clock synchronization scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analog and digital DLLs to align phases of two different frequency clocks. Simulation results represent that the internal clock is synchronized to the reference clock by tracking the dual feedback loop. The whole circuit design was performed using 0.35 μm CMOS technology. Power dissipation is about 42 mW at 320 MHz with a single 3.3 V supply

Keywords

CMOS integrated circuits; circuit feedback; delay lock loops; high-speed integrated circuits; mixed analogue-digital integrated circuits; synchronisation; 0.35 micron; 10 to 320 MHz; 3.3 V; 42 mW; CMOS technology; DLL based clock synchronizer; analog DLL; clock synchronization scheme; delay locked loop; digital DLL; dual feedback loop tracking; dual-loop DLL; internal clock synchronization; reference clock; Bandwidth; CMOS technology; Charge pumps; Clocks; Delay; Filters; Frequency synchronization; Phase locked loops; Stability; Tracking loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857415

Filename

857415