Title :
New approach to LUT implementation and accumulation for memory-based multiplication
Author :
Meher, Pramod Kumar
Author_Institution :
Commun. Syst. Dept., Agency for Sci., Technol. & Res. (A*STAR), Singapore, Singapore
Abstract :
A new approach to look-up-table (LUT) implementation for memory-based multiplication is presented, where the memory-size is reduced to half at the cost of some increase in combinational circuit complexity. The proposed design offers a saving of nearly 42% area and 38% area-delay product (ADP) at the cost of 6% increase in computational delay for memory-based multiplication of 8-bit inputs with 16-bit coefficient. For high-precision multiplication, a shift-save-accumulation scheme is proposed to accumulate the LUT outputs corresponding to the segments of input-operand, which requires nearly 1.5 times more area, but offers more than twice the throughput and nearly two-third the ADP of direct shift-accumulation approach.
Keywords :
circuit complexity; combinational circuits; digital arithmetic; integrated memory circuits; multiplying circuits; storage management; table lookup; LUT-based multiplier implementation; area-delay product; combinational circuit complexity; computational delay; direct shift-accumulation approach; high-precision multiplication; input-operand; look-up-table; memory-based multiplication; memory-size reduction; shift-save-accumulation scheme; Combinational circuits; Costs; Delay; Digital signal processing; Logic devices; Random access memory; Semiconductor memory; System-on-a-chip; Table lookup; Throughput;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117783
