Title :
A new architecture to compute the discrete cosine transform using the quadratic residue number system
Author :
Ramirez, J. ; Garcia, A. ; Fernández, P.G. ; Parrilla, L. ; Lloris, A.
Author_Institution :
Dept. of Electron. & Comput. Technol., Granada Univ., Spain
Abstract :
A new methodology to compute the N-point DCT (Discrete Cosine Transform) in the QRNS (Quadratic Residue Number System) is presented, with a significant improvement in complexity and speed compared to the corresponding binary version. This reduction in the total number of arithmetic adders and multipliers is up to 21% and 26% for an 8-point and a 16-point DCT, respectively. In addition, large and slow binary adders and multipliers with a long carry propagation delay are replaced by high-speed small word-length modular adders and LUT (Look-Up Table) multipliers. When a Field Programmable Logic (FPL) implementation using Altera FLEX10KE devices of the proposed architecture for the 8-point DCT is considered, throughput is three times better than that obtained with the corresponding fixed point 2´s complement binary implementation
Keywords :
adders; discrete cosine transforms; multiplying circuits; programmable logic devices; residue number systems; table lookup; Altera FLEX10KE; circuit architecture; digital arithmetic; discrete cosine transform; field programmable logic device; look-up table multiplier; modular adder; quadratic residue number system; Arithmetic; Computer architecture; Discrete Fourier transforms; Discrete cosine transforms; Image coding; Logic devices; Programmable logic arrays; Programmable logic devices; Table lookup; Transform coding;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857429
