A 24-Gb/s source-series terminated driver with inductor peaking in 28-nm CMOS

Author

Suzuki, Kenji ; Tomita, Yasumoto ; Yamaguchi, Hitoshi ; Tszshing Cheung ; Yamamoto, Takayuki ; Tamura, H.

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

2012

fDate

12-14 Nov. 2012

Firstpage

137

Lastpage

140

Abstract

We designed and tested a 24-Gb/s source-series terminated (SST) driver in 28-nm CMOS. The driver is composed of four segments with different weights to achieve an adjustable tap-weight finite-impulse-response (FIR) filter. The driver consists of nine slices, each of which contains four driver units. Each driver unit has a minimum-sized output stage regardless of the tap weight to reduce the power consumption of the preceding pre-driver stages. Series inductors connected to the output terminal of the driver are used to form a π-network circuit to enhance the bandwidth. The driver consumes 27.8 mW off a 0.85-V single supply. The total output jitter is 14.9 ps, which includes an input jitter of 11.1 ps. The core area is 330 × 330 μm2 with bumps.

Keywords

CMOS integrated circuits; FIR filters; driver circuits; inductors; integrated circuit design; integrated circuit testing; power integrated circuits; π-network circuit; CMOS technology; FIR; SST; adjustable tap-weight finite-impulse-response filter; bit rate 24 Gbit/s; jitter; power 27.8 mW; power consumption; series inductor; size 28 nm; source-series terminated driver; time 11.1 ps; time 14.9 ps; voltage 0.85 V;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian

Conference_Location

Kobe

Type

conf

DOI

10.1109/IPEC.2012.6522644

Filename

6522644