A novel algorithm for signed-digit online multiply-accumulate operation and its purely signed-binary hardware implementation

This paper presents a novel algorithm for purely signed-digit online multiply-accumulate (MAC) operation, and a corresponding architecture unit for a subsequent FPGA implementation using VHDL. In the proposed algorithm, a recursion formula for MAC operation is derived in terms of new input-independent variables (permitting a generalization of the algorithm to the evaluation of all affine functions), considering the relative positions of the MSDs of the signed-digit operands as design parameters. In a given iteration of the MAC algorithm, one adds an incoming partial result to the scaled error from the previous iteration, followed by estimating and generating a result digit, and saving an induced error. Context-free bounds on the internal variables are derived, and a lower bound on the latency is obtained in terms of various MAC operation parameters. The salient features of the proposed MAC architecture are that, (a) it offers the same input and output flow of digits as in practical analog-to-digital (A/D) and digital-to-analog (D/A) converters, (b) it permits a control of the precision of the result, and (c) it produces a MAC result that can be consumed by itself or by another online unit only after a small (constant) number of clock cycles. The correct functionality of the algorithm is confirmed through Matlab as well as Max+Plus II simulations