DocumentCode
2252049
Title
Redundant linear coding for accelerating counting and comparison operations
Author
Elhanany, I. ; Arazi, O.
Author_Institution
Dept. of Electr. & Comput. Eng., Ben-Gurion Univ. of the Negev, Beer-Sheva, Israel
Volume
5
fYear
2000
fDate
2000
Firstpage
333
Abstract
A novel binary number system, called Redundant Linear Coding (RLC), is presented. By eliminating the need for carry handling, a feasible tradeoff between speed and area yields short computation time for up/down counting and comparison operations. The scheme can efficiently be applied to a wide range of high-speed digital applications
Keywords
VLSI; carry logic; counting circuits; digital arithmetic; linear codes; redundancy; binary number system; comparison operations; high-speed digital applications; redundant linear coding; short computation time; up/down counting; Acceleration; Arithmetic; Correlators; Counting circuits; Logic design; Propagation delay; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location
Geneva
Print_ISBN
0-7803-5482-6
Type
conf
DOI
10.1109/ISCAS.2000.857432
Filename
857432
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