A hybrid segmentation and block processing algorithm for low power implementation of digital filters

The paper proposes a hierarchical algorithm for low power implementation of digital filters. The algorithm processes data and coefficients in blocks of fixed sizes. During the manipulation of each block, coefficients are segmented into two primitive components. The accumulative effect of processing a sequence of blocks and segmentation results in up to 80% reduction in power consumption compared to conventional filtering. The paper describes the implementation of the hierarchical algorithm, its constituent components and the power evaluation environment developed. Results are provided which demonstrate the effectiveness of the algorithm