Title :
A 0.05mm2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager
Author :
Jin-Yi Lin ; Hsin-Yuan Huang ; Chih-Cheng Hsieh ; Hung-i Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
This paper proposes a two-step switching SAR ADC architecture that greatly reduces the area and power consumption of the DAC network. The total number of unit capacitors of the proposed approach is only 64C. In addition, to reduce meta-stability at low-supply operation, a supply-boost technique of comparator is also employed. The prototype chip realized an 11-bit SAR ADC in a 0.18μm CMOS technology with an extremely small core area of 0.05mm2. With a single 0.6V supply voltage, the prototype consumes 5.02uW at 500kS/s, and achieves an ENOB of 9.45bit and a FoM of 14.34fJ/conversion-step, respectively.
Keywords :
CMOS image sensors; analogue-digital conversion; comparators (circuits); 3-dimensional stacking CMOS imager; CMOS technology; DAC network; area reduction; comparator supply-boost technique; meta-stability reduction; power 5.02 muW; power consumption reduction; size 0.18 mum; two-step switching SAR ADC architecture; unit capacitors; voltage 0.6 V;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522651
