• DocumentCode
    2252217
  • Title

    An ALU design using a novel asynchronous pipeline architecture

  • Author

    Tang, Tin-yau ; Choy, Chiu-Sing ; Butas, Jan ; Chan, Cheong-Fat

  • Author_Institution
    Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
  • Volume
    5
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    361
  • Abstract
    This paper presents a design of a 16-bit pipeline ALU. The ALU is implemented by using a novel asynchronous pipeline architecture. The architecture has simple handshake cells and these cells are embedded in the pipeline stage as normal logic cells. As a result, the speed of the ALU can be very fast
  • Keywords
    CMOS logic circuits; asynchronous circuits; cellular arrays; clocks; pipeline arithmetic; 16 bit; ALU design; asynchronous pipeline architecture; handshake cells; speed; Circuits; Clocks; Delay; Frequency; Logic; Pipelines; Protocols; Rails; Signal generators; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
  • Conference_Location
    Geneva
  • Print_ISBN
    0-7803-5482-6
  • Type

    conf

  • DOI
    10.1109/ISCAS.2000.857439
  • Filename
    857439
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2252217