An Analog Viterbi Decoder for PRML using Analog Parallel Processing Circuits of the CNN

An analog Viterbi decoder for the PRML signal is designed with the analog parallel processing circuits of the CNN. The PRML technology which is normally used for the high density storage device is incorporated with the multi-level coding and with the optimization technique of the Viterbi decoder. Since the PRML requires heavy computational load, the parallel processing structure of the CNN can be an efficient solution. In this paper, a CNN-based analog Viterbi decoder which is associated with a trellis diagram of PR(1,2,2,1) signal is fabricated into a chip. The test result of the chip is reported; its power consumption of the proposed one is 1/3 and its silicon area is 1/2 of its digital counter part while similar error correction performance is maintained