DocumentCode
2252404
Title
A simple mechanism to adapt leakage-control policies to temperature
Author
Kaxiras, Stefanos ; Xekalakis, Polychronis ; Keramidas, Georgios
Author_Institution
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
fYear
2005
fDate
8-10 Aug. 2005
Firstpage
54
Lastpage
59
Abstract
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so far that can be broadly categorized into state-preserving (e.g., drowsy caches) and nonstate preserving (e.g., cache decay). Decay saves more leakage but also incurs dynamic power overhead in the form of induced misses. Previous work has shown that depending on the leakage vs. dynamic power trade-off, one or the other technique can be better. Several factors such as cache architecture, technology parameters and temperature, affect this trade-off. Our work proposes the first mechanism - to the best of our knowledge - that takes into account temperature in adjusting the leakage control policy at run time. At very low temperatures, leakage is relatively weak so the need to tightly control it is not as important as the need to minimize extra dynamic power (e.g., decay-induced misses) or performance loss. We use a hybrid decay+drowsy policy where the main benefit comes from decaying cache lines while the drowsy mode is used to save leakage in long decay intervals. To adapt the decay mode to temperature, we propose a simple triggering mechanism that is based on the principles of decaying 4T thermal sensors and, as such, tied to temperature. The hotter the cache is, the faster cache lines are decayed since it is beneficial to do so with very high leakage currents. Conversely, when the cache temperature is low, our mechanism defers putting cache lines in decay mode to avoid dynamic power overhead but still saves a significant amount of leakage using the drowsy mode. Our study shows that across a wide range of temperatures, the simple adaptability of our proposal yields consistently better results than either the decay mode, or drowsy mode alone, improving over the best by as much as 33%.
Keywords
cache storage; integrated circuit reliability; integrated memory circuits; memory architecture; cache decay; cache memories; cache temperature; drowsy caches; dynamic power overhead; hybrid decay-drowsy policy; leakage control policy; leakage power reduction; nonstate preserving techniques; state-preserving techniques; Cache memory; Leakage current; Logic gates; Performance loss; Permission; Proposals; Temperature control; Temperature distribution; Temperature sensors; Thermal sensors;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN
1-59593-137-6
Type
conf
DOI
10.1109/LPE.2005.195485
Filename
1522734
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