Title :
Use of on-product measurements for process control for improved manufacturing efficiency and reduced costs
Author :
Cosway, Richard G. ; Ridens, Martin G. ; Peters, Megan ; Catmull, Kelvin ; Chilton, Shane R.
Author_Institution :
Die Manuf., Motorola Inc., Chandler, AZ, USA
Abstract :
With the increasing expense of cleanroom space, cost-effective wafer fabrication requires efficient use of that space and the minimization of non-value added activities as well as reducing the potential for scrap. To this end, minimization of test wafer usage provides multiple benefits through cost savings and improved efficiency. Historically, a number of in-line measurements have been performed on separate test wafers included with product wafers during diffusion processes. By performing these in-line measurements directly on product, a number of benefits accrue: (1) reduced test wafer cost. (2) reduced storage requirements. (3) reduced need for equipment to reclaim test wafers. (4) reduced need for direct labor to reclaim test wafers, and (5) reduced engineering “false alarms” due to incorrectly processed test wafers. In addition, quality improvements can be seen due to measurements being taken on actual product instead of separate non-product wafers. Implementation of on-product measurements for diffusion processes in a high-volume, 200-man factory has required a number of changes in both philosophy and methodology. These include addition of common scribe-grid process control (SGPC) structures on all production mask sets and procurement of all metrology tools with pattern-recognition capability. We will show the necessary steps to implementation with concern for overall manufacturing efficiency and the need to maintain appropriate control. Finally, we will comment on future requirements of metrology and process equipment to enable more widespread use of on-product measurements
Keywords :
clean rooms; economics; integrated circuit manufacture; integrated circuit testing; masks; pattern recognition; process control; production testing; quality control; cleanroom space; common scribe-grid process control; cost-effective wafer fabrication; false alarms; manufacturing costs; manufacturing efficiency; nonvalue added activities; on-product measurements; pattern-recognition capability; process control; product wafers; production mask sets; quality improvements; storage requirements; test wafer cost; test wafer usage; Costs; Diffusion processes; Fabrication; Manufacturing; Metrology; Performance evaluation; Process control; Procurement; Production facilities; Testing;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-3371-3
DOI :
10.1109/ASMC.1996.558086