Title :
A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13μm CMOS
Author :
Chen, Xinhua ; Huang, Qiuting
Author_Institution :
Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
Abstract :
A 4GHz integer-N frequency synthesizer is realized in a 0.13μm CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm2.
Keywords :
3G mobile communication; CMOS analogue integrated circuits; code division multiple access; frequency synthesizers; integrated circuit design; low-power electronics; microwave integrated circuits; transceivers; voltage-controlled oscillators; 0.13 micron; 2 GHz; 200 kHz; 4 GHz; 40 kHz; 400 kHz; 9.5 mW; CMOS integer-N frequency synthesizer; UMTS transceiver; VCO; WCDMA frequency synthesizer; charge sharing; reference spurs; self-regulated charge pump; Bandwidth; CMOS technology; Frequency conversion; Frequency locked loops; Frequency synthesizers; Multiaccess communication; Noise measurement; Phase measurement; Phase noise; Signal generators;
Conference_Titel :
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN :
1-59593-137-6
DOI :
10.1109/LPE.2005.195487
