DocumentCode
2252596
Title
A method for reducing the variation in “on” resistance of a MOS sampling switch
Author
Ong, A.K. ; Prodanov, V.I. ; Tarsia, M.
Author_Institution
Bell Labs., Lucent Technol. Bell Labs, Murray Hill, NJ, USA
Volume
5
fYear
2000
fDate
2000
Firstpage
437
Abstract
Variation in the “on” resistance of a MOS sampling switch can introduce distortion into the front end of a switched-capacitor filter or analog-to-digital converter. We review three methods commonly used to linearize the resistance of a MOS switch and propose a new technique that addresses their limitations. A practical method for implementation is also suggested
Keywords
MIS devices; field effect transistor switches; signal sampling; MOS sampling switch; analog-to-digital converter; distortion; front-end; linearization; on-resistance; switched capacitor filter; Bandwidth; Boosting; Breakdown voltage; Circuits; Immune system; MOS devices; Parasitic capacitance; Sampling methods; Switches; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location
Geneva
Print_ISBN
0-7803-5482-6
Type
conf
DOI
10.1109/ISCAS.2000.857465
Filename
857465
Link To Document