Low-power fanout optimization using multiple threshold voltage inverters

Author

Amelifard, Behnam ; Fallah, Farzan ; Pedram, Massoud

Author_Institution

Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA, USA

fYear

2005

fDate

8-10 Aug. 2005

Firstpage

95

Lastpage

98

Abstract

This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, power, and input capacitance, the fanout tree is converted to a set of inverter chains and for each chain the optimal sizes and threshold voltages are determined. Experimental results show that using this technique, the power dissipation of fanout tree is reduced by an average of 33% for a state-of-the-art CMOS technology.

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; invertors; low-power electronics; network topology; trees (mathematics); CMOS technology; delay preservation; fanout tree; integrated circuit design; low-power fanout optimization; multiple threshold voltage inverters; CMOS technology; Capacitance; Delay; Design optimization; Inverters; Libraries; Power dissipation; Semiconductor process modeling; Threshold voltage; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Print_ISBN

1-59593-137-6

Type

conf

DOI

10.1109/LPE.2005.195493

Filename

1522742