Linearity enhancement techniques for MOSFET-only SC circuits

Author

Leelavattananon, Kritsapon ; Toumazou, Chris ; Hughes, John B.

Author_Institution

Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK

Volume

5

fYear

2000

fDate

2000

Firstpage

453

Abstract

Techniques to enhance the linearity of switched-capacitor circuits utilising MOSFET gate capacitance are presented. Practical aspects limiting accuracy are investigated. With appropriate choice of capacitor technique, all types of switched-capacitor circuit become possible in standard digital CMOS processes. A sample-and-hold amplifier employing the proposed techniques was designed using a standard 0.6 μm digital CMOS process, and verified with simulation results to demonstrate significant linearity enhancement

Keywords

CMOS analogue integrated circuits; linearisation techniques; sample and hold circuits; switched capacitor networks; MOSFET gate capacitance; MOSFET-only SC circuits; accuracy limitation; linearity enhancement techniques; sample/hold amplifier; standard digital CMOS processes; switched-capacitor circuits; CMOS process; Capacitance; Delay; Educational institutions; Harmonic distortion; Laboratories; Linearity; MOSFET circuits; Switched capacitor circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857469

Filename

857469