A low-power, multichannel gated oscillator-based CDR for short-haul applications

Author

Tajalli, Armin ; Muller, Paul ; Atarodi, Mojtaba ; Lebiebici, Y.

Author_Institution

Sharif Univ. of Technol., Tehran, Iran

fYear

2005

fDate

8-10 Aug. 2005

Firstpage

107

Lastpage

110

Abstract

A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18μm digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8 V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51 mW/channel/Gbps while occupies 0.045mm² silicon area.

Keywords

CMOS digital integrated circuits; digital phase locked loops; jitter; low-power electronics; oscillators; transceivers; 0.18 micron; 1.8 V; 20 Gbit/s; 70.2 mW; bit error rate; data recovery system; digital CMOS technology; frequency offset tolerance; gated current controlled oscillator; jitter tolerance; low power multichannel clock; low power system; short haul; CMOS technology; Clocks; Energy consumption; Frequency; Jitter; Phase locked loops; Power system reliability; Silicon; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Print_ISBN

1-59593-137-6

Type

conf

DOI

10.1109/LPE.2005.195496

Filename

1522745