• DocumentCode
    2252721
  • Title

    A 1.2V 64fJ/conversion-step continuous-time ΣΔ modulator using asynchronous SAR quantizer and digital ΣΔ truncator

  • Author

    Hung-Chieh Tsai ; Chi-Lun Lo ; Chen-Yen Ho ; Yu-Hsin Lin

  • Author_Institution
    MediaTek Inc., Hsinchu, Taiwan
  • fYear
    2012
  • fDate
    12-14 Nov. 2012
  • Firstpage
    241
  • Lastpage
    244
  • Abstract
    A 3rd-order single-loop continuous time sigma-delta modulator (CTSDM) with 6-bit asynchronous SAR quantizer and digital delta-sigma truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed asynchronous SAR based quantizer reduces the area and power dramatically with the help of digital truncation technique. In addition, the modulator incorporating the proposed operational amplifiers (op-amp) with ac coupled push-pull stage is to improve the high frequency driving capability. The modulator sampling at 65MHz achieves 83.4dB dynamic range (DR) and 80/79.6dB peak SNR/SNDR with 1.92MHz bandwidth (BW) in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Implemented in 40nm CMOS, the modulator occupies 0.051mm2 and consumes 1.91mW from a 1.2V supply. A 64fJ/conversion figure of merit (FOM) is achieved.
  • Keywords
    3G mobile communication; CMOS integrated circuits; cellular radio; code division multiple access; operational amplifiers; quantisation (signal); sigma-delta modulation; AC coupled push-pull stage; CMOS; EDGE cellular systems; GSM cellular systems; WCDMA cellular systems; asynchronous SAR quantizer; bandwidth 1.92 MHz; continuous-time sigma-delta modulator; conversion-step sigma-delta modulator; digital delta-sigma truncator; operational amplifier; single-loop continuous time sigma-delta modulator; successive approximation register; voltage 1.2 V;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
  • Conference_Location
    Kobe
  • Type

    conf

  • DOI
    10.1109/IPEC.2012.6522670
  • Filename
    6522670