Cascaded carry-select adder (C2SA): a new structure for low-power CSA design

In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C²SA). Based on the prediction of the critical path delay of current operation, C²SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C²SA in 180nm technology show that C²SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.