Title :
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design
Author :
Chen, Yiran ; Li, Hai ; Roy, Kaushik ; Koh, Cheng-Kok
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C2SA). Based on the prediction of the critical path delay of current operation, C2SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C2SA in 180nm technology show that C2SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.
Keywords :
adders; carry logic; logic design; low-power electronics; 180 nm; 64 bit; C2SA; carry select adder; cascaded CSA; critical path delay; current operation; low power CSA design; post layout simulations; Adders; Circuit simulation; Clocks; Dynamic voltage scaling; Integrated circuit technology; Permission; Power dissipation; Propagation delay; Timing; Very large scale integration;
Conference_Titel :
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN :
1-59593-137-6
DOI :
10.1109/LPE.2005.195498
