Efficient implementation of intermediate frequency signal processor based on FPGA

Author

Fei, Zhu ; Shao, Zhen Hai

Author_Institution

High-tech Ind. Dev. Zone, Univ. of Electron. Sci. & Technol. of China, Cheng Du, China

fYear

2010

fDate

3-5 Dec. 2010

Firstpage

316

Lastpage

318

Abstract

This paper presents an available radio frequency signal processing unit software structure model. The model includes the direct frequency synthesis (DDS), down-sampling filter (CIC) and low pass filter (FIR). To reduce the hardware consumption and achieve high design efficiency, CAD tools were used and combined with specific and comprehensive VERILOG description. It can be seen from the results that IF signal processing unit in the xc4vsx25 in 200 MHz clock frequency is high-speed operated.

Keywords

field programmable gate arrays; frequency synthesizers; hardware description languages; logic CAD; low-pass filters; CAD tools; CIC; DDS; FIR; FPGA; IF signal processing unit; VERILOG description; direct frequency synthesis; down-sampling filter; field programmable gate arrays; frequency 200 MHz; intermediate frequency signal processor; low-pass filter; radiofrequency signal processing unit software structure model; Algorithm design and analysis; Band pass filters; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; IIR filters; CIC; DDS; FIR;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Problem-Solving (ICCP), 2010 International Conference on

Conference_Location

Lijiang

Print_ISBN

978-1-4244-8654-0

Type

conf

Filename

5695995