Statistical delay calculation with vector synthesis model

A statistical delay model for CMOS digital circuits called the “vector synthesis model” is proposed. The model provides a relationship between process random variables and a digital circuit path delay. A first order coefficient vector (FOCV), which characterizes the drain current of a transistor, is introduced as a characteristic parameter of the cell delay. The circuit path delay is modeled by synthesizing a FOCV of the path using the FOCVs of the cells constituting the path. The simple structure of the vector synthesis model enables the reduction of simulation cost for a statistical analysis. The accuracy of the vector synthesis model has been verified experimentally. The deviation of the worst case delay from the result by SPICE Monte Carlo analysis is around 5%, whereas that of an usual corner (slow-slow and fast-fast) analysis is as high as 25%