Power-optimal repeater insertion considering Vdd and Vth as design freedoms

This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and V_dd and V_th levels for a net with a delay target, and it reduces more than 50% power over a previous work which does not consider V_dd and V_th optimization. This work further presents the power saving when multiple V_dd and V_th levels are used in repeater insertion at the full-chip level. Compared to the case with single V_dd and V_th suggested by ITRS, optimized dual V_dd and dual V_th reduce overall global interconnect power by 47%, 28% and 13% for 130nm, 90nm and 65nm technology nodes, respectively, but extra V_dd or V_th levels only give marginal improvement. We also show that an optimized single V_th reduce interconnect power almost as effective as dual-V_th does, in contrast to the need of dual V_th for logic circuits.