• DocumentCode
    2252914
  • Title

    Linear programming for sizing, Vth and Vdd assignment

  • Author

    Chinnery, D.G. ; Keutzer, K.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    2005
  • fDate
    8-10 Aug. 2005
  • Firstpage
    149
  • Lastpage
    154
  • Abstract
    Most circuit sizing tools calculate the tradeoff between each gate´s delay and power or area, and then greedily change the gate with the best tradeoff. We show this is suboptimal. Instead we use a linear program to minimize circuit power. The linear program provides a fast and simultaneous analysis of how each gate affects gates it has a path to. Our approach reduces power by up to 30% compared to commercial software, with a 0.13μm library. The runtime for posing and solving the linear program scales linearly with circuit size.
  • Keywords
    circuit optimisation; delays; electronic engineering computing; integrated circuit design; linear programming; minimisation; 0.13 micron; circuit power minimization; circuit sizing tools; commercial software; linear programming; Circuits; Delay effects; Design optimization; Linear programming; Logic design; Permission; Power engineering computing; Runtime; Software algorithms; Software design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
  • Print_ISBN
    1-59593-137-6
  • Type

    conf

  • DOI
    10.1109/LPE.2005.195505
  • Filename
    1522754
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2252914