Title :
A multi-phase multi-frequency clock generator using superharmonic injection locked multipath ring oscillators as frequency dividers
Author :
Hafez, Amr Amin ; Ming-Shuan Chen ; Chih-Kong Ken Yang
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
A phase-locked loop providing multiphase clocks at 12-GHz and its subdivisions is presented. A quadrature VCO with low supply sensitivity is used. Frequency division is achieved using superharmonic injection-locked multipath ring oscillators to extend the maximum division frequency of latch-based dividers without using peaking inductors. A low mismatch charge pump reduces the reference spur level to a worst case of -74 dBc. The phase locked loop is fabricated in 65-nm CMOS. It operates in a frequency band between 7.92-12.14 GHz. The measured phase noise, random jitter, and power consumption at 12.08 GHz output frequency are -127.5 dBc/Hz at 10 MHz offset, 251 fs-rms, and 46.6 mW, respectively.
Keywords :
charge pump circuits; clocks; frequency dividers; injection locked oscillators; jitter; phase locked loops; phase noise; power consumption; CMOS; division frequency; frequency 7.92 GHz to 12.14 GHz; frequency band; frequency dividers; frequency division; latch-based dividers; low supply sensitivity; mismatch charge pump; multiphase clocks; multiphase multifrequency clock generator; output frequency; peaking inductors; phase locked loop; phase noise; phase-locked loop; power 46.6 mW; power consumption; quadrature VCO; random jitter; size 65 nm; spur level; superharmonic injection locked multipath ring oscillators; superharmonic injection-locked multipath ring oscillators;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522682
