Title :
A high-performance 1D-DCT architecture
Author :
Shams, Ahmed ; Pan, Wendi ; Chandanandan, Archana ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Sci., Louisiana Univ., Fayetteville, LA, USA
Abstract :
A high performance 1D-DCT is proposed. It is based on a new distributed arithmetic architecture technique (NEDA). Only addition operations are used, with 35 additions to complete the first phase of the computations. The final phase is the primitive add-and-shift operation. No subtraction, multiplication, or ROM are needed. High-throughput is achieved by pipelining the architecture. The delay of one stage is the delay of one 12-bit addition. Low power consumption is achieved by reducing the computation requirements compared to other implementations of the 1D-DCT
Keywords :
delays; discrete cosine transforms; distributed arithmetic; pipeline arithmetic; 1D-DCT architecture; addition operations; computation requirements; delay; new distributed arithmetic architecture technique; pipelining; power consumption; primitive add-and-shift operation; Arithmetic; Computer architecture; Delay; Discrete cosine transforms; Energy consumption; Hardware; Image coding; Read only memory; Signal processing algorithms; Transform coding;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857486
