A high-speed single-phase-clocked CMOS priority encoder

The maximum operating frequency of a priority encoder is usually limited by the long propagation delay of the priority token, and the delay will increase as the number of bit of the priority encoder increases. The concept of look-ahead can be applied to improve the performance. In this paper, the design of a high-speed priority encoder is presented. The main idea of this new design is a multi-level look-ahead structure, which can be realized efficiently by the single-phase-clocked dynamic CMOS logic. A 32-bit priority encoder is implemented in a 3 V, 0.6 μm CMOS technology to evaluate the performance of proposed techniques. The new priority encoder uses a 3-level look-ahead structure. As compared with the conventional design, the new design achieves 57% speed improvement with 5% layout area reduction