A 14 bit, 1 GS/s digital-to-analog converter with improved dynamic performances

This paper presents several novel approaches to improve the dynamic performance of a high-speed, high-resolution digital-to-analog converter (DAC). In order to improve the resolution of a 14-bit DAC, a double segmented decoding plus R-2R architecture is introduced. DAC system modeling shows that the dynamic performance of the DAC is strongly dependent on the output impedance of DAC current sources. The gain-boosting technique is applied to increase the output impedance of DAC current sources. A novel switch driver is introduced to further improve dynamic performance by isolating digital switching noise from the analog output. Multiple-level emitter coupled logic (MEL) is applied to the decoder logic due to its superior propagation time over emitter-coupled logic (ECL). The DAC circuit was designed using a 60 GHz f_T InGaP-GaAs HBT process. From circuit simulation, we find 0.62 LSB differential non-linearity (DNL), 0.71 LSB integral non-linearity (INL) and 1.25 ns settling time