Title :
A fast dynamic 64-bit comparator with small transistor count
Author :
Wang, Chua-Chin ; Wu, Hsin-Long ; Wu, Chih-Feng
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this paper, we propose a 64-bit fast dynamic CMOS comparator with a small transistor count. Major features of the proposed comparator are the rearrangement and re-ordering of transistors in the evaluation block of a dynamic cell, and the insertion of a weak n feedback inverter, which helps the pull-down operation to ground. The simulation results given by prelayout tools, e.g., HSPICE, and post-layout tools, e.g., TimeMill reveal that the delay is around 2.5 ns while the operating clock rate reaches 100 MHz
Keywords :
CMOS logic circuits; comparators (circuits); high-speed integrated circuits; 100 MHz; 2.5 ns; 64 bit; CMOS comparator; dynamic cell evaluation block; fast dynamic comparator; feedback inverter; pull-down operation; small transistor count; Automatic testing; CMOS logic circuits; Circuit simulation; Circuit testing; Clocks; Computational modeling; Inverters; Logic design; State feedback; Switches;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857492
