A 5.8GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution

A fully-integrated 5.8 GHz PLL modulator implemented in 65 nm CMOS achieves digitally-controlled arbitrary phase generation. The PLL consists of a Type II fractional-N PLL with a 1-bit TDC as its PFD. Digital phase setting, which operates by adding a proportional signal to the PFD output, is incorporated in the PLL. The prototype achieves an average phase resolution of 2.25o and a phase range of more than 720o. The entire PLL and output buffer consumes 11 mW.