Title :
A 5.8GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution
Author :
Li Li ; Flynn, Michael P. ; Ferriss, Mark A.
Author_Institution :
Electr. Eng., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
A fully-integrated 5.8 GHz PLL modulator implemented in 65 nm CMOS achieves digitally-controlled arbitrary phase generation. The PLL consists of a Type II fractional-N PLL with a 1-bit TDC as its PFD. Digital phase setting, which operates by adding a proportional signal to the PFD output, is incorporated in the PLL. The prototype achieves an average phase resolution of 2.25o and a phase range of more than 720o. The entire PLL and output buffer consumes 11 mW.
Keywords :
CMOS analogue integrated circuits; digital control; phase locked loops; CMOS; PFD; TDC; digital arbitrary phase-setting type II fractional-N PLL; digital phase setting; digitally-controlled arbitrary phase generation; frequency 5.8 GHz; fully-integrated PLL modulator; power 11 mW; size 65 nm; word length 1 bit;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522689
