DocumentCode :
2253182
Title :
High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar
Author :
Sumita, M.
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
fYear :
2005
fDate :
8-10 Aug. 2005
Firstpage :
203
Lastpage :
208
Abstract :
With scaling process generation, power management techniques are more significant. Body bias techniques are useful for the solutions. We propose a high resolution body bias generation circuit which supplies optimal body bias in both the active and standby mode. By using this circuit, the adjustment accuracy of threshold voltage (Vt) in the active mode was improved about 4.1 times of the conventional circuits at 0.6V forward body bias condition. In addition, for standby mode, when 128 kByte SRAM was supplied back body bias by this generator, the off-state leakage current was reduced to 50% of a fixed back body bias.
Keywords :
CMOS integrated circuits; SRAM chips; leakage currents; power supply circuits; CMOS scaling; SRAM; active mode; band to band tunneling; body bias generator; dead lock; forward body bias condition; high resolution body bias generation circuit; high resolution body bias technique; leakage components; leakage current; optimal body bias; parasitic bipolar; power management technique; process compensation; process variation; scaling process generation; standby mode; substrate bias; threshold voltage; CMOS process; Circuits; Delay; Energy consumption; Leakage current; Permission; Power generation; Standby generators; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN :
1-59593-137-6
Type :
conf
DOI :
10.1109/LPE.2005.195515
Filename :
1522764
Link To Document :
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