Title :
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
Author :
Garcia, Andrés ; Burleson, Wayne ; Danger, Jean Luc
Author_Institution :
Ecole Nat. Superieure des Telecommun., Paris, France
Abstract :
Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even if we increase silicon area. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage
Keywords :
VLSI; circuit optimisation; field programmable gate arrays; low-power electronics; parallel architectures; pipeline processing; FPGAs; VLSI; architectural optimization; low power digital design; pipeline architectures; power consumption; silicon area; supply voltage; Circuits; Clocks; Costs; Energy consumption; Field programmable gate arrays; Frequency; Low voltage; Pipelines; Power system reliability; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857496
