A 1 mW 10-bit 500KSPS SAR A/D converter

Author

Park, Jaejin ; Park, Ho-Jin ; Kim, Jae-Whui ; Seo, Sangnam ; Chung, Pau-Choo

Author_Institution

ASIC Dev. Team, Samsung Electron .Co., Yongin, South Korea

Volume

5

fYear

2000

fDate

2000

Firstpage

581

Abstract

A 1mW 1.5 V 10-bit 500 KSPS successive approximation (SAR) analog-to-digital converter (ADC) was fabricated in a 0.25 um CMOS technology. The capacitive and resistive digital-to-analog converter (DAC) with a track and hold (T/H) function can operate with low power consumption at a high conversion rate using the modified operating timing control. The proposed high accuracy comparator with open loop and closed loop offset compensation techniques can operate at a low supply voltage. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are i 0.7 LSB and i 1.25 LSB, respectively. The total power consumption is 1 mW at a 500 KSPS conversion rate with a 1.5 V single supply voltage in measurement results

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); digital-analogue conversion; low-power electronics; sample and hold circuits; 0.25 micron; 1 mW; 1.5 V; 10 bit; CMOS circuit; capacitive DAC; closed loop technique; comparator; differential nonlinearity; digital-to-analog converter; integral nonlinearity; low power operation; offset compensation; open loop technique; resistive DAC; successive approximation analog-to-digital converter; timing control; track-and-hold function; CMOS technology; Capacitors; Energy consumption; Low voltage; Open loop systems; Resistors; Sampling methods; Switches; Threshold voltage; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857501

Filename

857501