• DocumentCode
    2253342
  • Title

    Automatic pipelining from transactional datapath specifications

  • Author

    Nurvitadhi, Eriko ; Hoe, James C. ; Kam, Timothy ; Lu, Shih-Lien L.

  • Author_Institution
    Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    2010
  • fDate
    8-12 March 2010
  • Firstpage
    1001
  • Lastpage
    1004
  • Abstract
    We present a transactional datapath specification (T-spec) and the tool (T-piper) to synthesize automatically an in-order pipelined implementation from it. T-spec abstractly views a datapath as executing one transaction at a time, computing next system states based on current ones. From a T-spec, T-piper can synthesize a pipelined implementation that preserves original transaction semantics, while allowing simultaneous execution of multiple overlapped transactions across pipeline stages. T-piper not only ensures the correctness of pipelined executions, but can also employ forwarding and speculation to minimize performance loss due to data dependencies. Design case studies on RISC and CISC processor pipeline development are reported.
  • Keywords
    pipeline processing; reduced instruction set computing; CISC processor pipeline development; RISC; T-piper; T-spec; automatic pipelining; transactional datapath specifications; Clocks; Computer architecture; Design optimization; Feedback; Hazards; Logic design; Microarchitecture; Performance loss; Pipeline processing; Reduced instruction set computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-7054-9
  • Type

    conf

  • DOI
    10.1109/DATE.2010.5456900
  • Filename
    5456900