DocumentCode
2253351
Title
Single chip implementation of the 1.6 kbps speech vocoder
Author
Wang, Jia-Ching ; Wang, Jhing-Fa ; Chen, Han-Chiang
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
5
fYear
2000
fDate
2000
Firstpage
597
Abstract
In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch detection algorithm avoids the heavy computational load introduced by the traditional normalized autocorrelation method. The memory storing triangular function value is no longer needed after adopting the new LSP decoding process. The chip is designed with area effective feature and is suitable for stand alone application
Keywords
VLSI; decoding; interpolation; speech coding; vocoders; 1.6 kbit/s; LSP decoding; VLSI implementation; area effective feature; bit rate; computational load; heuristic pitch detection algorithm; interpolation property; memory storing triangular function value; normalized autocorrelation method; pitch detection; speech vocoder; synthesized speech; Autocorrelation; Bit rate; Decoding; Filters; Interpolation; Linear predictive coding; Speech coding; Speech synthesis; Very large scale integration; Vocoders;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location
Geneva
Print_ISBN
0-7803-5482-6
Type
conf
DOI
10.1109/ISCAS.2000.857506
Filename
857506
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