Title :
Higher radix Kogge-Stone parallel prefix adder architectures
Author :
Gurkayna, F.K. ; Leblebici, Yusuf ; Chaouat, Laurent ; McGuinness, Patrik J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
Abstract :
In this paper, we describe the design of radix-3 and radix-4 parallel prefix adders, that theoretically have logical depths of log 3n and log4n respectively, where n is the bit-width of the input signals. The main building blocks of the higher radix parallel prefix adders are identified and higher radix structures of Kogge-Stone Adders are presented. We show that with the higher radix architectures the logic depth can be reduced by 50% and the cell count can be reduced as much as 47% for 64-bit adders. Simulation results indicate that radix-4 adders can be more than 30% faster than radix-2 realizations
Keywords :
adders; digital arithmetic; 64 bit; Kogge-Stone parallel prefix adder; higher radix architecture; logic design; Adders; Binary trees; Buildings; Chaos; Computer architecture; Digital arithmetic; Digital signal processors; Logic; Signal design; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857516