Title :
Optimizing the number of parallel channels and the stage resolution in time interleaved pipeline A/D converters
Author :
Sumanen, Lauri ; Waltari, Mikko ; Halonen, Kari
Author_Institution :
Lab. of Electron. Design, Helsinki Univ. of Technol., Espoo, Finland
Abstract :
In this paper the effect of the number of parallel channels and the stage resolution on the sample rate and power dissipation of time interleaved parallel pipeline analog-to-digital converters (ADC´s) with identical stages are examined. Simple formulas are given to determine an optimum number of parallel channels and stage resolution for a given technology with respect to the conversion rate and current consumption. The formulas are applied for to 10 bit pipeline ADC using a standard 0.5 μm CMOS process parameters
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit optimisation; pipeline processing; 0.5 micron; 10 bit; CMOS process; analog-to-digital converters; conversion rate; current consumption; parallel channels number optimisation; pipeline A/D converters; power dissipation; sample rate; stage resolution optimisation; time interleaved pipeline ADC; Analog-digital conversion; CMOS process; Circuits; Clocks; Operational amplifiers; Pipelines; Power amplifiers; Power dissipation; Sampling methods; Signal resolution;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857518
