Overcoming the key barriers in 35 μm pitch wire bond packaging: probe, mold, and substrate solutions and trade-offs

Historically, the predominant obstacle to reducing wire bond pitch has been the positional accuracy and repeatability of the force and ultrasonics of the wire-bonding machine. However as the minimum bond pitch moved below 60 μm, new barriers have presented themselves. The barriers that are most frequently identified by semiconductor packaging engineers are those associated with probing the die, developing a suitable substrate in which to package it, and molding it without excessive yield loss due to wire sweep. This paper addresses the three key barriers that are enumerated above. It explores performance data and feasibility results from new or improved designs employing standard probing techniques and the feasibility of new ideas. Package substrate solutions-for various market segments are identified, and trade-offs in cost and performance are analyzed. Finally, the paper compares conventional corner gate molding to new molding techniques.