DocumentCode :
2253587
Title :
Approximate logic synthesis for error tolerant applications
Author :
Shin, Doochul ; Gupta, Sandeep K.
Author_Institution :
Electr. Eng. Dept., Univ. of Southern California, Los Angeles, CA, USA
fYear :
2010
fDate :
8-12 March 2010
Firstpage :
957
Lastpage :
960
Abstract :
Error tolerance formally captures the notion that - for a wide variety of applications including audio, video, graphics, and wireless communications - a defective chip that produces erroneous values at its outputs may be acceptable, provided the errors are of certain types and their severities are within application-specified thresholds. All previous research on error tolerance has focused on identifying such defective but acceptable chips during post-fabrication testing to improve yield. In this paper, we explore a completely new approach to exploit error tolerance based on the following observation: If certain deviations from the nominal output values are acceptable, then we can exploit this flexibility during circuit design to reduce circuit area and delay as well as to increase yield. The specific metric of error tolerance we focus on is error rate, i.e., how often the circuit produces erroneous outputs. We propose a new logic synthesis approach for the new problem of identifying how to exploit a given error rate threshold to maximally reduce the area of the synthesized circuit. Experiment results show that for an error rate threshold within 1%, our approach provides 9.43% literal reductions on average for all the benchmarks that we target.
Keywords :
logic circuits; logic design; network synthesis; approximate logic synthesis; audio application; circuit design; circuit synthesis; defective chip; error rate threshold; error tolerant application; graphics application; video application; wireless communication application; Circuit synthesis; Circuit testing; Complexity theory; Delay; Erbium; Error analysis; Fabrication; Graphics; Logic circuits; Wireless communication; approximate logic function; error tolerance; functional yield; logic synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
ISSN :
1530-1591
Print_ISBN :
978-1-4244-7054-9
Type :
conf
DOI :
10.1109/DATE.2010.5456913
Filename :
5456913
Link To Document :
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