Conductive interconnections through thick silicon substrates for 3D packaging

We have developed key technologies to form conductive interconnections through a thick silicon substrate, which are potentially applied for 3D device fabrication or packaging of optical MEMS devices. In this paper, we demonstrate to form metal filled Through-Holes (THs) in thick Silicon (Si) substrates (t=/spl sim/500 /spl mu/m) mainly using Photo Assisted Electro-Chemical Etching (PAECE) and Molten Metal Suctioned Method (MMSM). The THs that we experimentally made with these technologies had 15 /spl mu/m in the diameter and the aspect ratio of 35. And the maximum density was 500 THs/cm/sup 2/. The dielectric breakdown voltage of the THs was more than 500 V. In the result of a radioisotope leak test using Kr-85, the leakage rate of THs between the front and the back of the substrate was lower than the detection limit (1 /spl times/ 10/sup -15/ Pa/spl middot/m/sup 3//sec.).