• DocumentCode
    2253644
  • Title

    Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000

  • Author

    Li, Wei-Ming ; Hsia, Chih-Hsien ; Chiang, Jen-Shiun

  • Author_Institution
    Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
  • fYear
    2009
  • fDate
    24-27 May 2009
  • Firstpage
    750
  • Lastpage
    753
  • Abstract
    In this work, we propose a memory-efficient architecture of lifting based two-dimensional discrete wavelet transform (2D DWT) for motion-JPEG2000. The proposed 2D DWT architecture consists of a 1D row processor, internal memory, and a 1D column processor. The main advantage of this 2D DWT is to reduce the internal memory requirement significantly. For an NtimesN image, only 2N and 4N sizes of internal memory are required for the 5/3 and 9/7 filters, respectively, to perform the one-level 2D DWT decomposition. Moreover, it supports both lossless and lossy operation for 5/3 and 9/7 filters with high operation speed. The proposed 2D DWT surpasses the existed lifting-based designs in the aspects of low internal memory requirement. It is suitable for VLSI implementation and can support various real-time image/video applications such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
  • Keywords
    data compression; discrete wavelet transforms; filtering theory; image coding; image motion analysis; matrix decomposition; storage management; 1D column processor; 1D row processor; 2D DWT decomposition architecture; 2D dual-mode discrete wavelet transform; MPEG-4; VLSI implementation; filtering method; internal memory reduction; lifting-based design; matrix decomposition; memory-efficient architecture; motion-JPEG2000; texture object decoding; wavelet-based scalable video coding; Convolution; Convolutional codes; Discrete wavelet transforms; Electronic mail; Filters; Image coding; Memory architecture; Transform coding; Two dimensional displays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-3827-3
  • Electronic_ISBN
    978-1-4244-3828-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.2009.5117857
  • Filename
    5117857