Title :
Fast configurable-cache tuning with a unified second-level cache
Author :
Gordon-Ross, Ann ; Vahid, Frank ; Dutt, Nikil
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
Abstract :
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or a second level with separate instruction and data configurable caches. The authors instead used a commercially-common unified second level, a seemingly minor difference that actually expands the configuration space from 500 to about 20,000. Additive way tuning for tuning a cache subsystem was developed with this large space, yielding 62% energy savings and 35% performance improvements over a non-configurable cache, greatly outperforming an extension of a previous method.
Keywords :
cache storage; memory architecture; power consumption; reconfigurable architectures; cache memory; configurable cache tuning; memory hierarchy energy consumption reduction; unified second level cache; Application software; Cache memory; Computer science; Embedded computing; Embedded system; Energy consumption; Hardware; Microprocessors; Power engineering and energy; Space exploration;
Conference_Titel :
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN :
1-59593-137-6
DOI :
10.1109/LPE.2005.195540