A memory- and time-efficient on-chip TCAM minimizer for IP lookup

Ternary content addressable memories (TCAMs) are becoming very popular due to the simple-to-design IP lookup units included in high-speed routers; they are fast and simple to manage, and they provide a one-clock lookup solution. However, a major drawback of TCAM-based IP lookup schemes lies in their high power consumption. Thus, the rapid increase of routing tables inevitably deteriorates TCAM power efficiency. Although on-chip TCAM minimizers aim for the TCAM power efficiency in a fast time and at a small memory amount, the minimizers are not efficient in a large scale prefix table. In this paper, we present a hash-based on-chip TCAM minimization for a power- and throughput-efficient IP lookup. In a hash-based TCAM minimization (HTM), we convert prefixes into keys and merge keys with a fast hash lookup in an O(nW) complexity, where n is the number of prefixes and W is the number of IP bits. Additionally, by building a forest of merging trees and choosing a subset among them, we can achieve a higher minimization ratio. The simulation with two routing tables shows that our HPM scheme uses 8.6 and 4.0 times fewer computation time and memory, compared to a contemporary on-chip minimizer.