DocumentCode
2253890
Title
Parallel X-fault simulation with critical path tracing technique
Author
Ubar, Raimund ; Devadze, Sergei ; Raik, Jaan ; Jutman, Artur
Author_Institution
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
fYear
2010
fDate
8-12 March 2010
Firstpage
879
Lastpage
884
Abstract
In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.
Keywords
circuit simulation; fault simulation; logic testing; X-fault model; circuit fault detection; parallel X-fault simulation; parallel exact critical path fault tracing; stuck-at fault; two-phase procedure; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Electrical fault detection; Failure analysis; Fault diagnosis; Logic; Solid modeling; X-fault model; digital circuits; fault simulation; parallel exact critical path fault tracing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4244-7054-9
Type
conf
DOI
10.1109/DATE.2010.5456929
Filename
5456929
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