Title :
High performance VLSI implementation for H.264 Inter/Intra prediction
Author :
Alle, Mythri ; Biswas, J. ; Nandy, S.K.
Author_Institution :
CAD Lab., Indian Inst. of Sci., Bangalore
Abstract :
We provide a hardware realization of motion compensation and reconstruction (MCR) module for H.264 baseline profile. We synthesize the MCR module using UMC library in 0.13 mu CMOS technology. Our implementation occupies an area of 94756 gates and operates at a frequency of 250 MHz.
Keywords :
CMOS integrated circuits; VLSI; image reconstruction; motion compensation; video coding; 250 MHz; CMOS technology; H.264 baseline profile; H.264 inter-intra prediction; high performance VLSI implementation; motion compensation and reconstruction; CMOS technology; Finite impulse response filter; Frequency; Hardware; Interpolation; Libraries; Motion compensation; Pipelines; Registers; Very large scale integration;
Conference_Titel :
Consumer Electronics, 2007. ICCE 2007. Digest of Technical Papers. International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
1-4244-0763-X
Electronic_ISBN :
1-4244-0763-X
DOI :
10.1109/ICCE.2007.341385
