Title :
Achieving higher margins by solving the mobile flash test challenge
Author_Institution :
Credence Syst. Corp., Fremont, CA, USA
Abstract :
Manufacturers of flash memory are just beginning to realize the challenges that come with testing these devices. Given the low output current of sub-2 V devices, a significant issue is their limited ability to drive a capacitive load created by the test environment itself-due to high impedance. When it comes to speed test, the result can be that the test equipment characterizes the device as performing more slowly than it actually will perform in the application environment. A more accurate test method for low-power flash memory can be achieved by placing a unity gain follower circuit (buffer) as close to possible to the device under test, the capacitive load of the test environment can be all but eliminated from what the device sees and has to drive. This allows the device to be tested as it will eventually be used in the target application, giving a more accurate reading of the device´s true capability, thus producing better yield and profitability.
Keywords :
buffer circuits; capacitance; flash memories; integrated circuit economics; integrated circuit testing; integrated circuit yield; low-power electronics; test equipment; 2 V; DUT; accurate mobile flash memory testing; buffer circuits; capacitive load drive capability; device output current; device speed performance; device under test; device yield/profitability; high impedance test environment; low-power flash memory; production margins; speed tests; target application test conditions; test environment capacitive load; unity gain follower circuit; Batteries; Circuit testing; Digital cameras; Flash memory; Impedance; Manufacturing; Nonvolatile memory; Performance evaluation; Switches; System testing;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International
Print_ISBN :
0-7803-7301-4
DOI :
10.1109/IEMT.2002.1032789