An energy recovery approach for a charge redistribution successive approximation ADC

This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can then be stored for reuse, thus, provide a design approach for highly energy efficient ADC. The adiabatic switch is designed with two operation modes - Fast Switching Mode and Adiabatic Mode. Therefore, the ACCR DAC can operate at its fastest possible sampling rate during Fast Switching Mode and achieve highest energy efficiency during Adiabatic Mode. A 10-bit ACCR DAC using 0.18μm CMOS technology is simulated with SPICE. Simulation results show that the ACCR DAC achieves an energy efficiency of 30.42 fJ/conversion-step during Adiabatic Mode at a sampling rate of 100kS/s with 2V supply voltage. This is translated into an improvement of 69% as compared to the conventional switching method.