• DocumentCode
    2254788
  • Title

    An Image Recognition System for Multiple Video Inputs over a Multi-FPGA System

  • Author

    Otsuka, Takuya ; Aoki, Takashi ; Hosoya, Eiichi ; Onozawa, Akira

  • Author_Institution
    NTT Microsyst. Integration Labs., Atsugi, Japan
  • fYear
    2012
  • fDate
    20-22 Sept. 2012
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    A multi-user shared FPGA-based cloud computingplatform is presented for an image recognition application withmultiple video inputs. The platform is made of a sea of FPGAdevices, each connected as a hierarchical ring network. The users place IP cores called tiles on the platform and connect the tiles to each other to form a sequence. An architecture featuring aparallel pipeline of tiles and an intra-tile seIP cores called tiles on the platform and connect the tiles to each other to form a sequence. An architecture featuring aparallel pipeline of tiles and an intra-tile selector network isadopted so that users can work their own tile sequences in parallelwithout causing any interference with other users. A set ofapplication program interfaces (APIs) for writing tiles, deletingtiles, and configuring the intra-tile selector network isimplementedlector network isadopted so that users can work their own tile sequences in parallelwithout causing any interference with other users. A set ofapplication program interfaces (APIs) for writing tiles, deletingtiles, and configuring the intra-tile selector network isimplemented. With the APIs, the proposed system manipulatesthe tiles on FPGAs in response to users´ demands. The platform issuitable for running applications requiring low-latency andhigh-throughput data-processing capability. A histograms oforiented gradients feature extractor and Real AdaBoost classifierare implemented to perform image recognition.
  • Keywords
    application program interfaces; cloud computing; feature extraction; field programmable gate arrays; image classification; learning (artificial intelligence); logic circuits; microprocessor chips; video signal processing; API; AdaBoost classifier; IP cores; application program interfaces; hierarchical ring network; histograms of oriented gradients feature extractor; image recognition system; intratile selector network; lector network; low-latency andhigh-throughput data-processing capability; multiFPGA system; multiple video inputs; multiuser shared FPGA-based cloud computing platform; tile sequences; tiles pipeline; Bidirectional control; Computer architecture; Feature extraction; Field programmable gate arrays; Hardware; Streaming media; Tiles; AdaBoost; HOG; Image Recognition; Real Time System; Reconfigurable Platform;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded Multicore Socs (MCSoC), 2012 IEEE 6th International Symposium on
  • Conference_Location
    Aizu-Wakamatsu
  • Print_ISBN
    978-1-4673-2535-6
  • Electronic_ISBN
    978-0-7695-4800-5
  • Type

    conf

  • DOI
    10.1109/MCSoC.2012.33
  • Filename
    6354671