Title :
Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers
Author :
Tomabechi, Nobuhiro ; Ito, Teruki
Author_Institution :
Hachinohe Inst. of Technol., Japan
Abstract :
This paper proposes a design method of a high-speed RSA encryption processor in which the residue calculation of the redundant binary numbers is realized by table-look-up method where the table is built in the hardware, It is demonstrated that the number of gates through the critical path determining the operation speed of the proposed processor is 1/62 that of the conventional processors
Keywords :
high-speed integrated circuits; multiplying circuits; public key cryptography; redundant number systems; residue number systems; table lookup; built-in table; critical path; high-speed RSA encryption processor; operation speed; redundant binary numbers; residue calculation; table-look-up method; Arithmetic; Communication system security; Computer networks; Computer security; Cryptography; Data security; Design methodology; Hardware; Signal processing; Signal processing algorithms;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857583
